As AI data centers continue to grow, the demand for faster and more energy-efficient data transmission is increasing rapidly.
Traditional electrical interconnects are facing growing limitations in bandwidth, power consumption, and latency. This is one reason why Co-Packaged Optics (CPO) and silicon photonics are attracting increasing attention as next-generation interconnect technologies.
But there is a challenge that is often overlooked:
CPO may be ready for commercialization, but is CPO testing ready for mass production?
According to TrendForce, testing remains one of the key bottlenecks as CPO moves from the laboratory toward volume production. TSMC’s COUPE platform is also targeting volume production in 2026, further accelerating the development of the CPO ecosystem.
What Makes CPO Testing So Difficult?
Unlike traditional electronic IC testing, CPO combines electrical and optical technologies in the same package.
A typical CPO architecture integrates a Photonic Integrated Circuit (PIC) with an Electrical Integrated Circuit (EIC). The combined component is often referred to as an Optical Engine (OE).
The PIC may include:
Optical couplers
Modulators
Photodetectors
Optical filters
Optical waveguides
This means testing is no longer just about electrical performance.
Engineers also need to measure optical parameters such as:
Insertion Loss (IL)
Polarization-Dependent Loss (PDL)
Responsivity
Waveguide propagation loss
Optical crosstalk
The combination of electrical, optical, and optoelectronic testing makes CPO testing significantly more complicated than conventional IC testing.
The Alignment Problem
One of the biggest challenges is optical alignment.
Light needs to travel from an external optical fiber into an extremely small optical waveguide. The difference in physical size is enormous.
According to TrendForce, the cross-sectional area of a single-mode fiber core is approximately 78.5 µm², while the optical waveguide can be around 0.099 µm².
That means the fiber core can be hundreds of times larger than the waveguide.
Even a small positioning error can result in significant coupling loss.
This is why CPO testing requires extremely precise alignment, together with advanced optical probes, machine vision, and automated positioning systems.
Today, some of these processes still involve significant manual operations. TrendForce estimates that 100% inspection of a single PIC can take more than 100 seconds, creating a major challenge for high-volume manufacturing.
Four Key Stages of CPO Testing
CPO testing does not happen at just one stage. The process can generally be divided into four major levels.
1. PIC Wafer-Level Testing
The first stage focuses on the photonic integrated circuit itself.
Typical measurements include:
DC electrical performance
Optical power
Optical loss
Dark current
This stage is especially important because defective PICs can be identified before they are bonded with expensive EICs.
2. EIC-PIC Wafer-Level Testing
The next stage combines electrical and optical testing.
Testing may include:
Electro-optical performance
Opto-electrical performance
High-speed testing
S-parameter measurements
3. Optical Engine Testing
At the Optical Engine level, testing becomes more comprehensive.
It can include:
- DC testing
High-speed testing
Calibration
Optical loopback testing
S-parameter measurements
This stage helps identify Known Good Optical Engines (KGOE)before further assembly.
4. Advanced Package and Module Testing
The final stage focuses on the complete module.
The goal is to verify:
System-level functionality
Optical performance
High-speed communication
Optical loopback performance
Why OWAT Could Be the Most Important Stage
Among these testing stages, Optical Wafer Acceptance Test (OWAT)is particularly important.
The reason is simple:
Find defects early.
PICs are generally manufactured using relatively mature process nodes, while EICs can involve much more expensive advanced-node processes.
If a defective PIC is discovered only after it has already been bonded with an expensive EIC, the resulting loss can be significant.
Early wafer-level testing can therefore help reduce:
EIC scrap
Packaging losses
Testing costs
Manufacturing time
For CPO to reach high-volume production, improving wafer-level optical testing and automation will be critical.
Who Is Building the CPO Testing Ecosystem?
The CPO testing market is attracting companies from several parts of the semiconductor equipment industry.
Traditional ATE leaders such as Advantest and Teradyne are expanding into photonic testing through partnerships and acquisitions.
At the same time, companies such as FormFactor, Keysight, Chroma, ficonTEC, and Enlitech are developing optical probing, measurement, alignment, and reliability-testing solutions.
For example, Advantest and FormFactor have worked on photonic testing solutions featuring advanced optical alignment capabilities.
Teradyne and ficonTEC have also developed wafer-level and die-level testing solutions for silicon photonics.
Meanwhile, Keysight brings high-speed measurement and optical characterization technologies into the CPO testing ecosystem.
These developments show that CPO testing is becoming a multidisciplinary market rather than a traditional ATE market alone.
CPO Testing Is Becoming a New Semiconductor Opportunity
The growth of AI is pushing the semiconductor industry beyond computing performance.
Interconnect performance is becoming equally important.
As AI clusters become larger, moving massive amounts of data between GPUs, switches, memory, and other components creates increasing bandwidth and power challenges.
This is one of the reasons why CPO is attracting attention.
TrendForce expects CPO and NPO markets to expand significantly as AI infrastructure continues to scale, with the combined market projected to exceed US$39 billion by 2030.
But before CPO can reach true mass production, the industry still needs to solve several critical problems:
Better alignment.
Higher testing speed.
More automation.
Lower testing costs.
More standardized testing methods.
Final Thoughts
CPO is no longer just a laboratory concept.
As AI data centers demand higher bandwidth and lower power consumption, optical interconnects are becoming an increasingly important part of the semiconductor ecosystem.
However, building the technology is only one part of the challenge.
The ability to test it quickly, accurately, and economically may ultimately determine how fast CPO can scale.
For semiconductor manufacturers, equipment suppliers, component companies, and supply-chain partners, CPO testing is an area worth watching closely.
The next breakthrough in AI infrastructure may not only come from faster chips.
It may come from better ways to test and connect them.
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